Oct 22, 2026 · 1h 9m
AI demand collides with semiconductor manufacturing limits
What will computer chips look like in 2045?
The episode shows why future compute growth depends not only on transistor design, but also on tools, materials, factories, and capital.
- 1Advanced nodes now hinge on yield learning, equipment availability, and integration discipline as much as transistor breakthroughs.
- 2CFETs, backside power, new interconnects, and hybrid bonding could extend scaling, but heat and manufacturing complexity set hard limits.
- 3AI demand is exposing bottlenecks across fabs, memory, equipment, power, water, and the economics of capacity expansion.
Don't miss
The Hot Topics meeting reveals how Intel decides which process problems receive scarce wafers and engineering resources.
The brief
AI has created semiconductor demand on a scale that collides with scarce EUV tools, limited fab capacity, and the long timelines required to expand production.
Chris Auth explains how Intel develops and matures a process such as 14A, while revisiting the 10-nanometer delay and the engineering cost of aggressive scaling.
The technical frontier moves from High-NA EUV and backside power to CFETs, new interconnect materials, and hybrid bonding—but every advance adds integration and thermal challenges.
At Intel’s Hot Topics meeting, Kevin Fisher shows how engineers prioritize scarce wafers and experiments, turning manufacturing problems into a disciplined race for evidence.
The episode’s broader argument is economic: sustained AI growth requires the entire equipment and supply chain to scale, not merely better chip designs.
What was said on this episode
15 statements · 10 positive · 3 negative · 1 mixed · 1 neutral
AI demand exceeds semiconductor computing capacity by 40–50%.
“AI is driving incredible computing demand, easily 40 to 50% above our maximum capacity, which I've never seen before.”
Listen at 0:06
Intel 10-nanometer technology has world-class yield, performance, and cost.
“10-nanometer is a great technology. It has world-class yield, it has world-class performance, it has world-class cost”
Listen at 4:29
Gate-all-around is the ultimate transistor structure.
“gate-all-round's really the ultimate transistor out there.”
Listen at 10:36
The number of semiconductor materials used has increased roughly tenfold since the 1990s.
“It's probably gone up 10x”
Listen at 12:52
High-NA EUV is highly useful for Intel's backside-power architecture.
“For us, it is very helpful.”
Listen at 15:14
The industry’s move toward gate-all-around transistors was somewhat inevitable.
“I think where we've gotten to, you know, as far as the transistor and gate-all-around and it being the ideal transistor structure that I have, I think was somewhat inevitable.”
Listen at 19:38
The tightest interconnect pitches will eventually replace copper.
“I think for some of the very tightest pitches, I think it's inevitable that you will replace copper.”
Listen at 20:14
Copper will remain suitable for larger interconnect lines.
“But for the larger lines, I think copper is about where it's at.”
Listen at 20:23
By 2045, semiconductor chips could contain exotic three-dimensional structures.
“2045, do you think you could do it? Uh, and now you start to say, oh yeah, I could see having some pretty exotic structures at that point.”
Listen at 21:20
Thermal dissipation limits current and future computing systems.
“it is a limiter and it will be a limiter.”
Listen at 23:28
Ruthenium outperforms copper at roughly 20-nanometer interconnect pitch.
“there is a crossover point that ruthenium will have much better conductivity, better resistivity than copper, And that's roughly in the 20-nanometer pitch range”
Listen at 30:37
CFET is the ultimate transistor architecture for stacking.
“It is the ultimate in stackability.”
Listen at 33:05
CFET requires about 1,000 integrated steps to match or exceed prior technology.
“there's 1,000 different steps that all have to come together in a very unique way to make the performance compatible or actually supersede the prior technology.”
Listen at 38:12
Intel hybrid bonding has reached sub-10-micrometer pitch in development.
“Today in HVM, we're doing 25 micrometer pitch in Foveros. Here we're doing sub-10”
Listen at 45:44
Finer hybrid-bonded interconnects reduce interface power consumption.
“as you get to finer and finer interconnects, you can reduce the total power consumption in picojoules per bit for that interface.”
Listen at 47:39
Statements are attributed to the speaker as said on the episode and reflect their view at the time, not PodLume's. They are not advice.
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